Verification in Networked Embedded Systems ∗

Compared to test or simulation, formal verification poses an attractive way by either guaranteeing the correctness of the system or generating a counter example to indicate the violation. However, due to state explosion, the power of formal verification is usually restricted to trivial systems. This project is motivated by two observations of Networked Embedded Systems: a) due to limited physical resources, device’s behavior is simple and is implemented in elegant codes, and b) usually all devices are the same, i.e., the system is highly symmetric. These yield two advantages while adopting formal verification: a) a concise formal model may be achieved and b)symmetry reduction may be applied. Both alleviate state explosion problem. In this manner, large-scale system may be verifiable.